V groove MOS transistors are described by Y. Tarui, et al in an article entitled "Diffusion Self-Aligned MOST: a New Approach for a High Speed Device" appearing in the Proceedings of the First Conference on Solid State Devices, Tokyo, 1969. The Tarui device, shown in FIG. 1, is formed by a surface diffused n-type source and a buried n-type drain spaced thereunder. Electrical contact is made to the buried drain by an n-type diffused column. A p-type high conductivity base layer and a p-type low conductivity space charge region (shown as a drift region in FIG. 1) are provided between the source and the drain. Appropriate lead contacts are made along the top of the device to the gate, source, and drain elements. The Tarui prior art device has several notable drawbacks. First, the area required to provide surface lead contacts to the three elements takes up by far the majority of the chip surface area. Each of these three conductive leads occupies a terminal space immediately above each element, and also a conducting path space, across the surface of the chip to another device or circuit. Secondly, the buried drain and diffused drain contact are awkward to form with present industrial practices, and may increase the internal resistance of the Tarui device. Thirdly, a high drain-to-substrate capacitance is created by the heavily doped n-type drain immediately adjacent to the p-type substrate. This critical capacitance is further increased by the large interface between the drain and the substrate and the drain and the space charge region.